SYSTEM/65 DESIGN DETAILS

This is the area where the details and schematics for the system will be displayed. I'm very gradually figuring out how to put it together as I learn more about digital logic, so things are going to be fairly incomplete for a while yet.


I have more or less figured out how to do address decoding and memory mapping, I think. As I noted on the Memory Mapping page, I have Chris Ward to thank for introducing me to the use of de-multiplexers in address decoding; the rest I've more or less figured out myself.

The first step of address decoding is done with a 74138 3:8 de-multiplexer, using A12-A14 from the CPU as inputs and A15 for output enable; this divides up the top half of CPU address space into eight 4KB chunks, each of which gets a select signal from the de-multiplexer. (The bottom half of CPU address space is handled by the RAM bank selectors, which are explained below.) The bottom four select lines are tied together to provide a select line for the common RAM area. The fifth selects the expansion area, and the sixth selects the I/O area. The top two select lines are tied together to provide a select line for the EEPROM.

The EEPROM is hooked up with just a simple straight-across connection to A0-A12 of the CPU. The expansion area is also quite simple; A0-A11, the expansion select line, and any unused select lines from the I/O area are run out onto the expansion connector. The I/O area and common RAM are slightly more complex.

The I/O area is handled by a 74154 4:16 de-multiplexer, which uses A8-A11 of the CPU for inputs and the I/O select line from the 3:8 de-multiplexer for output enable. This divides the 4KB I/O area into 16 256-byte chunks. Each of these corresponds to an output from the de-multiplexer, which is used as a chip-select line for the appropriate device, with the necessary number of address lines connected to the register select lines for the chip.

Device 0 in the I/O area is used to address the control registers for the custom parts of the computer. Currently, there are only two registers here, the two bank selectors for the memory mapper. These are held in 74377 octal D-type flip-flops. Register 0 controls the stack select, and register 1 controls the bank select. The write-enable line for each register is provided by NANDing together the write-enable line from the CPU, the I/O select line for the register area, and A0 from the CPU (for register 0) or A0 inverted (for register 1.)

The common RAM area is just as simple as the EEPROM: the appropriate lines from the 74138 are tied into two select lines, one for each 8KB RAM chip, and the necessary address lines (A0-A12) are run straight through to the chips.

The banked RAM area consists of two separate areas, the zero page/stack area (from $0000-01FF,) and the banked RAM proper (from $0200-7FFF.) These are controlled by selectors which work essentially like an 8086-style segment register. The area of banked RAM is determined by running A9-A14 through a 744075 triple three-input OR gate array; if any of these lines are high, the result will be high. The output from the last OR gate is used as the selector to two 74257 quadruple 2:1 multiplexer, which is used to select between the stack and banked RAM bank selectors. The output of the multiplexer is fed into one operand of a pair of 74283 4-bit adders chained together into one 8-bit adder; the low six bits of the other operand are provided from A9-A14 of the CPU. The 8-bit result is used as A9-A16 of the SRAM address, while A0-A8 are run straight through from the CPU.