ADDRESSING MODES

There are a variety of addressing modes that the CPU can use when fetching data from memory. In keeping with the goal of instruction-set orthogonality, most addressing modes can be used with any instruction; the only exceptions to this are where it would make no sense (Store Immediate, for example,) or where the eight opcodes reserved for each instruction are taken up by more vital addressing modes.


MEMORY-ACCESS MODES

Dummy
Dummy instructions do not have either a specified address or a register as their destination; instead, the value read is discarded. In all other respects, the instruction behaves normally.

Immediate
Immediate instructions are the inverse of dummy instructions, in that the source for the data is neither a specified address or register. Instead, the value read comes in the instruction post-word.

Memory
Memory instructions affect an address in memory specified by the instruction post-word.

Register
Register instructions affect a CPU register specified by the instruction post-byte.

Indirect
Indirect instructions affect an address in memory pointed to by the value at the address specified in the instruction post-word.

Register indirect
Register indirect instructions affect an address in memory pointed to by the value of a CPU register specified in the instruction post-byte.

Indexed
Indexed instructions affect an address in memory specified by the sum of the instruction post-word and the CPU register specified in the instruction post-byte.

Indexed++
Indexed post-increment instructions affect an address in memory specified by the sum of the instruction post-word and the CPU register specified in the instruction post-byte. Afterwards, the index register is incremented.

Indexed--
Indexed post-decrement instructions affect an address in memory specified by the sum of the instruction post-word and the CPU register specified in the instruction post-byte. Afterwards, the index register is decremented.

Indirect indexed
Indirect indexed instructions affect an address in memory specified by the sum of the value at the address specified in the instruction post-word and the CPU register specified in the instruction post-byte.


FLOW-CONTROL MODES

Next (+2)
Next instructions add 2 to the PC register, skipping the instruction immediately following.

Absolute
Absolute instructions load the PC register with the instruction post-word, effecting a jump within the current segment.

Absolute far
Absolute far instructions load the CS register with the instruction post-byte and the PC register with the instruction post-word, effecting a jump to any segment of memory.

Relative
Relative instructions load the PC register with the sum of its current value and a signed 16-bit value loaded from the instruction post-word, effecting a jump relative to the position immediately after the instruction post-word.

Indirect
Indirect instructions load the PC register with the value in memory pointed at by the instruction post-word.