INTERRUPTS

The CPU has a total of eight different interrupts. Seven of these are triggered by external sources, and all of them can be triggered as software interrupts. The vectors for these interrupts are located at physical addresses 0x7FFF0-7FFFF in memory, and are two words long, the first word containing the segment selector, and the second containing the address:

0x0-1Int0
0x2-3Int1
0x4-5Int2
0x6-7Int3
0x8-9Int4
0xA-BInt5
0xC-DInt6 (Exception)
0xE-FInt7 (Reset)

Interrupts are prioritized in descending order; that is, the higher-numbered interrupts have priority over the lower-numbered interrupts. As you can see, this means that the Reset and Exception interrupts have the highest priority in the CPU; this is because they are the only two special interrupts. Reset is, obviously, used to reset the system, and Exception is used to inform the program when various errors internal to the CPU have occurred. The Exception interrupt is the only one not connected to an external interrupt-request line. Neither special interrupt can be masked with the I bit in the status register.

The Exception interrupt is triggered on any error internal to the CPU. The nature of the error is indicated by flags in the SF register. The A flag indicates an Address exception, meaning that address arithmetic caused an overflow past the boundaries of the 19-bit address bus. The U flag indicates that the CPU tried to executed an unimplemented opcode. If neither flag is set, it means that a program initiated the Exception interrupt through software.

When an interrupt occurs, the CPU first pushes the SF register to the stack, then the PC register, then the CS register. After these have been pushed, the new values for the CS and PC registers are loaded from the interrupt-vector table, and execution is transferred to the interrupt handler.